The present invention is directed to a circuit for voltage multiplication of the type having a level converter connected to an inverter stage with a first stage containing a first capacitor, a first inverter stage and first and second transistors.
Hearing aids of the prior art contain a plurality of individual components such as, for example, low-noise preamplifiers, switched capacitor filter circuits as well as a voltage supply part. In order to improve the signal-to-noise ratio in battery-operated "switched capacitor" filter circuits (SC filter circuits), the modulation range of the filter circuit can be increased by doubling the supply voltage. The supply voltage of hearing aids usually is in the range of 1-1.5 volts, so that a doubling to 2-3 volts with additional battery cells causes additional difficulties because of the spatially tight conditions in a hearing aid housing.
The technical literature discloses a number of voltage multiplier circuits specifically for the hearing aid field such as, for example, "a 1.5 volt single-supply one-transistor CMOS EEProm" by B. Gerber et al, IEEE, Sc-16, No. 3, June 1981, pages 195-199 and "On Chip High Voltage Generation In NMOS-Integrated Circuits Using An Improved Voltage Multiplier Technique", by John F. Dickson, IEEE, Sc-11, No. 3, June 1976, pages 374-378, as well as "Inductance-Less Up DC-DC Converter", by S. Singer, IEEE Sc-17, No. 4, August 1982, pages 778 through 780. All of these prior art voltage multiplier circuits use diodes or transistors connected as diodes. A voltage multiplier circuit for low voltages, however, is advantageously constructed with transistor circuits. Since a diode only becomes conductive when the threshold voltage is exceeded, the supply voltage must lie above this threshold voltage by a multiple in such a circuit in order for a voltage boost to occur. By contrast, a transistor in an on-state can be viewed as a low-impedance resistor along which no voltage drop is present after a charge balancing has occurred. German Patent Application Serial No. P 33 45 423.5 "Schaltung Zur Spannungsvervielfachung" discloses a voltage multiplier circuit in CMOS technology. For a given voltage, this circuit generates a positive voltage in loss-free no-load operation that is twice as high.
FIG. 3 in the publication of F. Callias et al, "A Set of 4 IC's in CMOS-Technology for a programmable hearing aid", IEEE, 1988, Custom Integrated Circuit Conference, pages 2-5, discloses a voltage tripling circuit in CMOS technology wherein a negative voltage is generated for a given positive voltage. In FIG. 3 of the publication, the voltage tripling circuit has a level converter, a drive circuit and a three-stage capacitor network, whereby the drive circuit is connected between the level converter and the three-stage capacitor network.